Showcasing advanced hardware IP design, RISC-V verification, automation, and AI datasets.
Designed and implemented AES hardware IP supporting 128-bit, 192-bit, and 256-bit key lengths with modular RTL architecture and pipelining. Developed comprehensive UVM testbenches and utilized formal tools (JasperGold) to verify FIPS-197 compliance and encryption symmetry.
Implemented and validated custom RISC-V Vector ISA extensions supporting accelerated parallel arithmetic, dot products, and matrix multiplication. Created directed assembly test suites and random instruction generators for thorough corner-case validation.
Developed automation solutions using SystemRDL 2.0 to generate synthesizable RTL register blocks, UVM RAL models, and documentation. Created conversion scripts and contributed to open-source RDL-to-RAL toolchain evaluations.
Curated high-quality training datasets for Large Language Models covering Verilog/SystemVerilog RTL development, UVM testbench automation, SystemVerilog Assertions (SVA), coverage closure, and automated hardware debugging scenarios.
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